1. Technical Field of the Invention
The present invention relates to semiconductor devices including miniaturized dielectric gate type transistors, and more particularly to a MIS transistor having an LDD (Lightly Doped Drain) structure, in other words extension regions and a method for fabricating the same.
2. Conventional Technology
With the progress in higher large-scale integration and miniaturization of semiconductor integrated circuits, step up operations with lower power supply voltages are required. Under such circumstances, MIS transistors (Field Effect MIS transistors: MISFETs) generally adopt LDD structure.
The LDD structure is also called an extension region of source/drain. As is well known, low concentration regions in source/drain regions are formed in advance by injecting impurity ions by using a region of the gate electrode as a mask prior to forming sidewalls on the gate electrode. With further miniaturization of MOS transistors, the low concentration regions (extension regions) of the source/drain regions have become shallower.
Also, the impurity concentration in channel sections of MOS transistors tends to be increased to a higher concentration level to counter a fear of the short channel effect and to restrain punch through effects. In addition, as a more advanced counter measure, so called pocket ions may be injected.
The pocket ion injection forms impurity regions of an opposite conductive type to that of the source/drain regions at least below low concentration extension regions (i.e., pocket ion injection regions). This prevents the punch through phenomenon, and suppresses leak currents across the source and the drain.
Pocket ion injection regions may be formed in a stage, for example, before or after the extension regions are formed, by injecting ions. Ions may be injected through a resist pattern. The pocket ion injection regions may also be called “Holo regions”.
FIG. 8 shows a cross-sectional view of a structure of a conventional MIS transistor. A gate electrode 84 is formed through a gate oxide film 83 over a channel region 82 in, for example, a P-type element region 81 of a semiconductor substrate. N-type source/drain regions 87 that are separated from each other across a channel region are formed in the semiconductor substrate below both ends of the gate electrode 84.
The source/drain region 87 is formed from a low concentration N-type impurity region (N− region) 871 and a high concentration N-type impurity region (N+ region) 872. Prior to forming sidewall dielectric films 86 at the gate electrode 84, the N− regions 871 are formed in advance as an LDD structure, i.e., extension regions by injecting ions using a region of the gate electrode 84 as a mask.
When the sidewall dielectric films 86 are formed, since the material of the sidewall dielectric films 86 (for example, silicon oxide films or silicon nitride films) and the semiconductor substrate have a low selective ratio in etching, the semiconductor substrate may be over-etched.
In this case, if the extension regions (N− regions 871) are shallowly formed, the source/drain regions 87, there is a great danger that the source/drain regions 87 become discontinuous in sections encircled by broken lines at the low concentration N-type impurity regions (N− regions) 871 and the high concentration N-type impurity regions (N+ regions) 872. As a result, the electrical resistance value across the impurity regions 871 and 872 increases, and thus it is feared that the transistor performance deteriorates. Also, this over-etching may cause in not a few occasions situations in which the N− regions 871 below the sidewalls are almost eliminated. As a countermeasure, the extension regions (N− regions 871) may be formed deeper. However, this is not a technique appropriate for the miniaturization, and therefore is not very much preferred.
Also, to prevent punch through, P-type high concentration impurity regions (pocket ion injected regions) of an opposite conductive type to that of the source/drain regions may be formed in areas indicated by broken lines below the extension regions. In this case, a measure to limit the concentration (suppress to a lower level) of the pocket ion injected regions also needs to be taken into consideration. In other words, this is needed to stably obtain the N− regions 871 and N+ regions 872 without a fear that they become discontinuous. However, this is not a technique appropriate for the miniaturization, either, and therefore is not very much preferred.
The present invention has been made in view of the circumstances described above, and its object is to provide miniaturized MIS transistors that are highly reliable and can effectively suppress punch through, and a method for fabricating the same.